TL;DR #
In a validated 4-pack parallel BESS configuration running at a 400 V bus, SOP-weighted power allocation held inter-pack SOC deviation to within 10% across full charge and discharge cycles, with current imbalance staying under 1% relative deviation at matched SOC. For buyers procuring multi-pack residential or C&I storage systems, this means the balancing architecture — not cell chemistry alone — determines whether your system reaches full capacity utilization or suffers premature cutoff on the weakest pack. Before issuing an RFQ, require suppliers to demonstrate autonomous SOC equalization test data across a minimum 2-cycle full charge/discharge sequence with SOC spread logged.
Overview #
If you’ve ever watched a multi-pack storage system cut off early because one pack hit its SOC floor while the others still had 30% remaining, you already understand why parallel SOC equalization is one of the most undervalued specifications in residential and light commercial BESS procurement. Most buyers focus on cell chemistry and BMS protection features — and miss the control architecture entirely.
The methodology evaluated here comes from engineering validation work conducted on a representative home energy storage platform: a 4-pack parallel system at 400 V high-side bus voltage, each pack integrating a built-in DCDC converter, BMS, and CAN communication stack. The test program covered multiple full charge/discharge cycles with SOC-spread conditions introduced to stress the equalization response. Pack-level power, bus voltage, and current were logged throughout.
The core approach — distributing charge/discharge power proportionally to each pack’s SOP (State of Power) rather than using passive voltage droop alone — produced measurably better end-of-cycle alignment than conventional droop-only methods. The finding has direct implications for how buyers should evaluate BESS topologies, especially in applications where packs may be added incrementally or replaced individually over system lifetime.
SOP-Weighted Power Distribution in Parallel Battery Pack Systems #
The fundamental problem with naive parallel operation is straightforward: packs with different SOC levels will have different terminal voltages, and without active intervention, the pack with the highest voltage dominates discharge while the one with the lowest voltage gets overcharged first. Voltage droop control helps, but it’s a reactive mechanism — it responds to current imbalance after it develops.
The SOP-weighted approach flips this. Each pack continuously broadcasts its current power (Pow(i)) and its maximum allowable charge/discharge power (PowReq(i)) over a dedicated CAN2 bus at a 250 kbps baud rate. Every 100 milliseconds, each pack independently recalculates the system’s total power (PowTotal) and demand power (PowReqTotal) from the broadcast data, then derives its own target power (PowTarget(i)) as its SOP fraction of PowTotal.
The power loop itself is a PI controller whose output is a bus voltage trim ΔV — a small adjustment layered onto the local bus voltage setpoint. During discharge, raising ΔV increases local output power. During charge, the sign convention reverses: a more negative target power drives ΔV negative, lowering the bus voltage setpoint to pull in more charging current. The constraint on ΔV is deliberately tight — it’s set slightly wider than the bus voltage measurement noise floor to avoid amplifying sensor error into circulating current.
| Parameter | Specification | Design Rationale |
|---|---|---|
| CAN bus baud rate | 250 kbps | Matches GB/T charging pile national standard frame format |
| Broadcast cycle | 100 ms | SOP changes slowly; 100 ms refresh adequate for loop stability |
| Per-frame transmission time | ~0.45 ms | 4-pack system total bus load well within arbitration window |
| SOC equalization target | ≤10% max deviation | Validated across 2 full charge/discharge cycles |
| Current imbalance (matched SOC) | <1% relative deviation | Tested at multiple load levels via resistive load bank |
| Bus voltage | 400 V (high side) | Typical residential/light C&I BESS architecture |
| Pack operating states | 1 = running, 0 = standby | Standby packs excluded from equalization calculation |
| ΔV adjustment range | Slightly above sampling noise floor | Prevents large circulating currents while allowing effective trim |
The peer-to-peer broadcast architecture — no master pack, no central controller — is a meaningful design choice. Each pack runs an identical algorithm. If one pack drops off the bus, the remaining packs recalculate PowTotal from the next broadcast cycle without any reconfiguration. This is exactly the kind of fault-tolerant topology that matters in field-deployed systems where individual pack replacement is routine.

Validated SOC Equalization Performance Across Full Charge/Discharge Cycles #
This is where the engineering data gets concrete.
Under matched SOC conditions (all four packs starting at the same SOC), current balance at the pack level was measured at multiple discharge power levels using a resistive load bank. The maximum relative current deviation across all four packs stayed within 1% — confirming that the SOP weighting degenerates correctly to equal distribution when SOP values are equal. That’s a useful sanity check: the algorithm doesn’t introduce artificial imbalance when packs are already balanced.
The more demanding test is what happens with SOC spread. Over two complete charge/discharge cycles logged with SOC waveforms, the maximum SOC deviation between any two packs peaked at approximately 10%. Critically, both the charge-end tail and the discharge-end tail equalized fully — all four packs reached 100% SOC at end of charge and 0% SOC at end of discharge. This end-of-cycle convergence is the whole point. A system that maintains 10% mid-cycle spread but converges completely at both endpoints effectively uses 100% of its installed capacity.
Honestly, most procurement teams don’t fully appreciate the difference between mid-cycle SOC deviation and end-of-cycle equalization. A 10% mid-cycle spread sounds like a spec failure until you see that it converges to zero at both endpoints — at which point it’s actually a well-tuned system. The spec that matters is end-state alignment, not instantaneous spread.


In supplier qualification work, we’ve seen systems that claim SOC balancing but can’t demonstrate end-of-cycle convergence. The supplier shows you a flat mid-cycle SOC trace and calls it balanced — but that’s often because they’ve set aggressive current limiting that prevents the weak pack from ever diverging, not because the algorithm is working. Ask for the full waveform, not a snapshot.
Most procurement teams don’t realize that SOC equalization requirements were significantly tightened in recent revisions to residential BESS safety and performance standards. Current field evaluation practice — including work reflected in IEC 62619 industrial safety requirements and UL 9540 system-level certification — increasingly expects demonstrable capacity utilization data across multi-pack configurations, not just single-pack BMS protection evidence.
Communication Architecture and Autonomous Control Design #
The dual-CAN structure deserves attention from buyers evaluating BESS communication architecture. External CAN1 handles pack-to-PCS communication — this is the interface buyers typically see documented in product specs. Internal CAN2, running at 250 kbps between DCDC modules, carries the equalization data: pack address (Add(i)), operating state (Stat(i)), current power (Pow(i)), SOP, and debug telemetry including battery voltage (BatV), battery current (BatI), bus voltage (BusV), and bus current (BusI).
The CAN frame IDs are structured for broadcast: 0x1966FFxx carries equalization data (Stat, Pow, PowReq); 0x1967FFxx carries electrical debug telemetry; 0x196AFFxx carries algorithm state (PowTarget, SOC). The FF in the target address field designates broadcast — every pack receives every other pack’s frame each 100 ms cycle. CAN’s built-in arbitration handles collision avoidance by ID priority, and the hardware-level error retry mechanism ensures reliable delivery without application-layer acknowledgment overhead.
This matters for buyers because it defines the debug and serviceability story. The system was designed for a USB-CAN monitoring tool that can be hung on the CAN2 bus to display all pack states simultaneously on a PC — a practical requirement for field commissioning and fault diagnosis that buyers should verify is supported before purchase, not after installation.
For standards alignment, the CAN frame format was designed to match GB/T 27930 — the Chinese national standard for communication between off-board chargers and BMS. Buyers targeting IEC or UL markets should confirm whether this frame format creates any compliance mapping issues with their target certification path under IEC 62619 or UN 38.3 transport requirements.
Honestly, the autonomous peer-to-peer equalization design is underappreciated in procurement evaluations. Buyers routinely ask “does it have BMS balancing?” without distinguishing between a passive cell-level balancing resistor network and a full autonomous pack-level SOC equalization architecture. These are not the same thing. The former handles cell drift within a pack; the latter handles capacity utilization across packs in a multi-pack system. If you’re specifying a multi-pack installation, you need both.
Practical Guidance for Buyers #
For multi-pack BESS procurement, the single most costly oversight is treating SOC equalization as a checkbox rather than a testable performance parameter. Require suppliers to provide logged SOC data — not a specification sheet value, but actual waveform data — from a minimum 2-cycle charge/discharge test on a multi-pack configuration matching your intended deployment. The data should show SOC spread per pack at mid-cycle and convergence status at end-of-charge and end-of-discharge.
Second, clarify the communication architecture. A DCDC-integrated pack with autonomous peer-to-peer equalization over a dedicated CAN bus is a meaningfully different product from a passive parallel pack relying on voltage matching. The former can compensate for incremental pack addition and gradual SOC divergence over field lifetime; the latter cannot. Ask specifically whether the equalization algorithm requires a master controller or operates independently on each pack — the answer tells you a lot about fault tolerance and serviceability.
For residential and light C&I applications targeting European or North American markets, verify that the CAN communication protocol can be mapped to your target certification framework. Systems designed to GB/T 27930 may require protocol adaptation for full IEC 62619 or UL 9540 compliance documentation.
At compactbess.com, we work directly with verified Chinese manufacturers of multi-pack BESS systems and can help you identify suppliers who have already validated autonomous SOC equalization architectures on 400 V parallel platforms. If you’re evaluating residential or light C&I storage configurations and need suppliers who can provide actual test data — not just spec sheets — our sourcing team can match you with qualified options.
Need help identifying qualified suppliers for parallel BESS with autonomous SOC equalization? Talk to our sourcing team →
Supplier Qualification Questions #
- Can you provide logged SOC waveform data from a minimum 2-cycle full charge/discharge test on your multi-pack system, showing both mid-cycle SOC spread and end-of-cycle convergence — with maximum deviation documented at ≤10%?
- What is the inter-pack current balance deviation at matched SOC conditions across your parallel pack configuration, and can you provide load bank test data showing relative current deviation under multiple discharge power levels?
- Does your equalization architecture operate autonomously on each pack using peer-to-peer broadcast (no master controller), and what is the CAN broadcast cycle time and baud rate for the internal DCDC equalization bus?
- What is the ΔV adjustment range your power loop uses to trim bus voltage for equalization, and how is it set relative to your bus voltage ADC sampling precision to prevent circulating currents?
- How does your system handle a mid-deployment pack replacement or incremental pack addition — does the equalization algorithm automatically detect and include the new pack’s SOP in the next 100 ms broadcast cycle without manual reconfiguration?
Sourcing Checklist #
- [ ] Supplier provides SOC deviation waveform data across ≥2 full charge/discharge cycles showing maximum inter-pack SOC spread ≤10%
- [ ] End-of-charge equalization verified: all packs reach 100% SOC within the same charge cycle with convergence documented
- [ ] End-of-discharge equalization verified: all packs reach 0% SOC within the same discharge cycle without premature cutoff on any pack
- [ ] Current balance data shows ≤1% relative deviation between packs at matched SOC under resistive load bank test conditions
- [ ] CAN equalization bus operates at 250 kbps with ≤100 ms broadcast cycle and confirmed hardware arbitration and error-retry mechanisms
- [ ] Pack operating state flag (run/standby) confirmed functional — standby packs excluded from equalization calculation to prevent algorithm errors
- [ ] Communication protocol documentation provided for both external PCS-facing CAN and internal DCDC equalization CAN, with frame ID map
- [ ] System supports USB-CAN or equivalent bus monitoring tool for field commissioning and fault diagnosis across all packs simultaneously
Key Specifications Table #
| Parameter | Recommended Value | Verification Method |
|---|---|---|
| Inter-pack SOC deviation (mid-cycle) | ≤10% maximum | SOC waveform logging across ≥2 full charge/discharge cycles with initial SOC spread |
| Inter-pack current balance (matched SOC) | <1% relative deviation | Resistive load bank test at multiple discharge power levels, 4-pack configuration |
| CAN equalization broadcast cycle | 100 ms | Protocol analyzer or USB-CAN bus monitor — verify frame timestamps |
| CAN baud rate (internal equalization bus) | 250 kbps | Bus analyzer confirmation; verify against GB/T 27930 frame format compliance |
| Bus voltage trim range (ΔV) | Slightly above ADC noise floor (supplier to specify) | Request ADC resolution spec and confirm ΔV limits are set within ±1–2 LSB of noise floor |
| Pack SOP broadcast data | Pow(i), PowReq(i), Stat(i) per pack per cycle | CAN frame decode — verify 0x1966FFxx frame contains all three fields per pack |
Can’t find a supplier meeting these specs? Submit your requirements and we’ll match you within 48 hours.
Frequently Asked Questions #
Q: What is the difference between cell-level balancing and pack-level SOC equalization in a multi-pack BESS?
Cell-level balancing (passive resistor bleed or active charge shuttle circuits within a BMS) addresses voltage and capacity differences between individual cells inside a single pack. Pack-level SOC equalization, as described here, addresses power distribution differences between multiple packs wired in parallel — a system-level concern that a single-pack BMS cannot solve. You need both in a multi-pack deployment: cell balancing keeps each pack healthy internally, while pack-level equalization ensures the system uses all packs to their full capacity.
Q: Why does the system use a dedicated second CAN bus for equalization rather than the main PCS communication bus?
Separating the equalization CAN (CAN2) from the PCS interface (CAN1) isolates algorithm-critical timing from PCS protocol overhead and prevents equalization broadcast traffic from competing with inverter control commands. It also allows the equalization loop to continue operating if the PCS communication link is interrupted — a meaningful fault-tolerance benefit in field conditions.
Q: Is a 10% mid-cycle SOC deviation acceptable for residential BESS applications?
Yes, provided end-of-cycle convergence is confirmed. The 10% figure represents peak spread during active charge or discharge, not a persistent imbalance. If all packs converge to 100% at end-of-charge and 0% at end-of-discharge, the system is utilizing full installed capacity. The 10% mid-cycle spread is a consequence of the proportional power allocation working correctly — packs with more SOP headroom absorb or deliver more power transiently.
Q: Can this equalization approach handle a mixed-age pack scenario where one pack has degraded capacity?
The SOP-weighted algorithm inherently accommodates degraded packs: a pack with reduced capacity will report a lower SOP, receive a proportionally smaller power allocation, and reach its charge/discharge endpoint at roughly the same time as healthier packs. This is more graceful than voltage-droop-only systems, which tend to either overwork degraded packs or lock them out entirely.
Q: What happens if one pack loses CAN communication during operation?
Each pack runs the equalization algorithm locally using the last-received broadcast data. A pack that stops broadcasting will, after a missed-cycle timeout, be excluded from other packs’ PowReqTotal calculation — equivalent to the standby state (Stat = 0). The remaining packs redistribute the total power among themselves in the next 100 ms cycle. Buyers should confirm the specific timeout threshold and fallback behavior with the supplier during qualification.
For related technical content on BMS communication architectures, see our BMS Communication Protocols guide and SOC Estimation Methods documentation.
Published by compactbess.com Technical Team | Request a sourcing quote
Data source: Autonomous SOC Equalization in Parallel-Connected Battery Packs Using SOP-Weighted Power Distribution and DCDC Bus Voltage Control, L. Liu et al., Journal of the Electrochemical Society, 2024
Content reviewed by elena.fischer | © compactbess.com — All rights reserved. Unauthorized reproduction prohibited.