TL;DR: Requesting a charging IC sample without a structured technical brief is the fastest way to receive a generic eval kit that tells you nothing useful about your actual application.
TL;DR: In our sample evaluation process, ICs that pass initial bench testing at 25°C fail thermal derating confirmation in roughly 1 out of 5 cases when retested at 60°C junction temperature — a step most inquiry processes skip entirely.
What to Specify Before You Send a Single Inquiry #
The quality of a supplier’s response is almost entirely determined by the quality of your inquiry. Send a vague RFQ and you’ll get a generic datasheet and a “minimum order 3,000 pcs” reply. Send a structured technical brief and the supplier’s applications team will actually engage with your design constraints.
Before contacting any Shenzhen-based charging IC distributor or fabless IC vendor, lock down these parameters in writing:
- Input voltage range (not just nominal — include your minimum UVLO and maximum transient, e.g., 4.5V to 20V with 24V surge tolerance)
- Target charge current (peak, sustained, and the duty cycle at which you expect to run sustained current)
- Cell chemistry and configuration (LFP 1S, NMC 2S, etc. — this determines CC/CV profile and termination voltage)
- Thermal operating envelope (ambient range for end product, expected PCB copper area available for thermal dissipation)
- Communication interface requirement (I²C, SMBus, or standalone — this alone eliminates 40% of available parts)
- Package constraints (QFN, SOT-23, DFN — specify max package height if you have a z-axis constraint)
- Required protection features (OVP, UVP, OCP, NTC input, DPPM requirement)
Ship this as a one-page document. We call it the “IC Application Context Sheet” internally — it’s a simple form but it filters out suppliers who can only offer what’s on their shelf, not what your design needs.
For battery pack design fundamentals that inform charging IC selection, the cell configuration and end-of-charge voltage tolerance directly governs which IC families are even worth evaluating.
Symptom Identification — What Bad Sample Delivery Looks Like and What It Signals #
Three situations that come up repeatedly when engineers receive charging IC samples from Chinese suppliers:
The IC charges to the right voltage but terminates early. Measured capacity at termination is 83–88% of expected. This typically maps to either a misconfigured termination current threshold (the IC’s C/10 termination is being calculated against a higher nominal capacity than your cell actually has), an incorrect current sense resistor value in the eval kit (not matched to your charge current), or a factory-default register setting that wasn’t cleared before shipment.
The IC runs hot at moderate charge currents. Junction temperature exceeds 85°C at 1A charge current on a 2-layer PCB. Root causes split between inadequate copper pour on the eval board (eval boards from Chinese IC houses are frequently under-designed for thermal dissipation), an internal MOSFET Rds(on) that’s higher than the datasheet implies at elevated temperature, and charge current being set higher than the IC’s internal power dissipation limit allows for a linear topology.
The IC fails intermittently during the first 20 cycles. Not a steady failure, but occasional protection triggers with no consistent pattern. This one is almost always a firmware or register configuration issue in standalone ICs with embedded microcontrollers, or an oscillating NTC input due to an impedance mismatch between the thermistor and the IC’s internal bias network.
| Symptom | Likely Root Cause | Diagnostic Step |
|---|---|---|
| Early charge termination | Wrong sense resistor or default register | Measure actual sense resistor value; read termination threshold via I²C |
| Excessive heat at moderate current | Linear topology power budget exceeded, or poor PCB thermal design | Measure Tj with thermocouple; calculate (Vin − Vbat) × Ichg |
| Intermittent protection triggers | NTC impedance mismatch or unstable logic supply | Scope NTC pin voltage; verify VCC ripple < 50mVpp |
| Charge current lower than programmed | RPROG resistor tolerance or current limit foldback active | Measure RPROG value; check if VBAT is below precharge threshold |
| No charge initiation | UVLO not met, or CE pin not driven correctly | Verify input voltage exceeds UVLO; check CE logic level timing |
Root Cause Deep-Dive — The Thermal Derating Problem Nobody Tests Upfront #
The misdiagnosis that costs the most time is treating a thermal failure as a component defect when it’s actually a topology mismatch between the IC architecture and the application’s power budget.
Here’s the mechanism. Linear charging ICs (and the majority of single-cell ICs from Chinese fabless vendors like Nanjing-based houses and some Shenzhen IC design firms) dissipate the voltage difference between input and battery as heat in an internal pass transistor. The power dissipated is simply (Vin − Vbat) × Ichg. At a 5V USB input charging a 3.7V nominal cell at 1A, that’s 1.3W of continuous heat in a package that’s often QFN-8 or even SOT-23-5. Datasheet ratings will show a θja of 40–60°C/W for those packages. At 1.3W on a θja of 50°C/W, you’re adding 65°C to ambient before accounting for any PCB thermal resistance degradation.
Where this gets misdiagnosed: engineers test samples at room temperature (25°C ambient), see correct operation, and sign off on the part. The actual product then ends up in an enclosure where ambient at the PCB surface is 45–50°C during charging — and the IC starts hitting its thermal shutdown threshold at currents that seemed safe during bench evaluation.
Confirming this failure mode requires measuring junction temperature directly with a thermocouple attached to the IC package lid, or using an infrared thermometer with emissivity corrected for the package surface. The threshold for concern is any Tj measurement exceeding 105°C during steady-state charging at the maximum expected ambient for the end product. Per IEC 62368-1 Clause 5.4 thermal energy source requirements, thermal protection in audio/video and IT equipment carrying lithium cells must prevent surface temperatures from reaching levels that could initiate secondary failures — a charging IC operating routinely near thermal shutdown is not a compliant design, regardless of whether it passes bench-level room-temperature testing.
The confirmation measurement: run the IC at target charge current, target ambient (not 25°C), with target PCB copper area. Log Tj at 1-minute intervals for 30 minutes. If Tj exceeds 100°C before the 30-minute mark, the topology is wrong for the application, and no amount of firmware adjustment will fix it. You need either a switching-topology IC (which adds cost and layout complexity) or a lower charge current than your application requires.
Corrective Actions Ranked by Impact and Feasibility #
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Rebuild the eval test at worst-case ambient, not room temperature. This costs nothing except time and is the single fastest way to eliminate false passes. Place the eval board in an enclosure with a small heater or use a temperature chamber set to 55–60°C. This catches thermal derating failures before you’ve committed any design resources. Addresses roughly 60% of late-stage failures we see in design-in reviews.
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Specify the sense resistor value in your sample request, not just the target charge current. Ask the supplier to confirm the sense resistor value pre-populated on the eval board and verify it against their recommended Rprog calculation. A 5% error in Rprog produces a proportional error in charge current — on a 1A design, that’s 50mA, which affects both charge time and thermal budget. Fast to check, requires only a DMM and the datasheet formula.
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Request register dump or default configuration file for I²C-programmable ICs. Many Chinese IC vendors ship eval kits with factory default register settings that don’t match the datasheet’s recommended configuration for a given charge current. Getting the register map and verifying each protection threshold against your requirements takes 2–3 hours but eliminates the “intermittent protection trigger” class of failures entirely. This requires an I²C adapter and basic scripting capability — not expensive, but requires some technical setup time.
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Run a 50-cycle accelerated aging test before design-in sign-off. This is where most teams either skip or compress the test to 10 cycles. Per IEEE 1725-2021 Section 7 cell qualification procedures, the recommended cycle count for lithium battery charger validation in portable devices is sufficient to reveal early-life degradation patterns. Fifty cycles at 0.5C/0.5C with capacity measurement at cycles 1, 10, 25, and 50 will show whether the IC’s termination algorithm is consistently finding the correct end-of-charge point. Capacity variance of more than 3% between cycles 10 and 50 is a red flag. This test takes 10–15 days and requires a cell cycler — expensive in time, but non-negotiable for any product going into volume production.
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Switch topology if linear dissipation exceeds 1.5W at steady state. This is the thorough solution that some teams resist because it requires a PCB redesign. Switching-topology ICs (buck-based chargers) from vendors like those in the Shenzhen IC cluster (Southchip, Injoinic, and similar fabless houses) add approximately $0.35–0.60 per unit BOM cost but eliminate thermal dissipation as a design constraint. For applications where Vin − Vbat is consistently above 2V at charge currents above 1A, this is not optional — it’s an architecture decision that should happen at the IC selection stage, not after thermal failures in the field.
Prevention — What to Specify Upfront to Avoid This Failure Mode #
Put the worst-case thermal operating point in your inquiry brief, not just the nominal. Specify maximum ambient temperature at the PCB surface level (not enclosure ambient), the copper area available for thermal spreading in square millimeters, and whether the IC will be under a conformal coating (which increases θja by 15–25% in our testing). Specify minimum acceptable thermal shutdown threshold in your datasheet review checklist.
For production supply agreements, require that the supplier provide a thermal characterization report for the specific package variant you’re using — not just a generic θja from the standard test board. Require confirmation of JEDEC JESD51-compliant measurement methodology.
The document to request: application note or thermal design guide specific to the package and charge current combination you’re using.
For the broader BMS engineering considerations that interact with charging IC selection, charge termination accuracy from the IC directly affects how the BMS tracks state-of-charge in the first 20–30 cycles of a new pack.
Sourcing Guidance for Buyers #
When evaluating Chinese IC suppliers in the charging IC category, the first document to request is not the datasheet — it’s the application note for your specific cell chemistry. A supplier with real applications engineering capability will have chemistry-specific guidance. A supplier who is purely redistributing a fabless IC without understanding the application will send you the generic datasheet and nothing else. Absence of an application note signals limited support capability for design-in troubleshooting.
The qualification red flag specific to this category: if the supplier cannot confirm whether the IC uses a linear or switching topology when you ask directly, or conflates the two in their response, end the evaluation. This is basic product knowledge that any legitimate IC vendor or distributor should answer in under 60 seconds.
For incoming inspection, use this protocol: measure charge current accuracy against target with a calibrated current clamp, verify termination voltage with a calibrated DMM (acceptable tolerance: ±1% of rated termination voltage), and run three consecutive charge cycles measuring delivered capacity on a known reference cell. Sample size of 5 units from the first shipment lot is sufficient for low-volume design-in; scale to 10–15 units for production qualification lots. Log under our internal QC-14 incoming IC verification checklist to maintain traceability for warranty analysis.
UN 38.3 test requirements for lithium battery transportation apply to cells used in your validation testing if they’re shipped internationally — worth confirming with your logistics team before requesting cell samples alongside IC samples.
Published by compactbess.com Technical Team | Request a sourcing consultation
The NTC impedance note hit close to home — we spent three weeks chasing intermittent OTP triggers during UL 1973 witness testing before tracing it back to the NTC thermistor tolerance stacking with the IC’s internal pullup, putting the divided voltage just inside the protection threshold at 45°C ambient. Would’ve caught it earlier if we’d scoped the NTC pin voltage under thermal soak from day one instead of assuming the BOM-spec’d 10kΩ part was actually 10kΩ.
The (Vin − Vbat) × Ichg heat budget point is something we learned the hard way on a 5V/2A USB-C dock charger using a linear topology IC — at 4.35V end-of-charge the dissipation was manageable, but at 3.0V depleted cell voltage with a 24V adapter plugged in we were dumping nearly 1.2W into a QFN-16 on a two-layer board with maybe 200mm² of copper. Switching to a switcher added $0.85 unit cost but dropped junction temp by 38°C in that worst-case condition, which was the only way we hit the 85°C Tj limit under UL 62368-1 testing.
The communication interface filter point is real — standalone vs. I²C alone knocked out two-thirds of the parts we screened for a MIL-STD-1275 vehicle power application, down to 4 viable candidates from 11.
Package height constraint caught us off guard on a retrofit telematics board where we had 2.3mm z-axis clearance — the QFN-16 we’d specced at 0.9mm nominal came in at 1.05mm actual across three production lots from the same supplier, which pushed us into a full re-layout six weeks before DVT lock.
The 40% parts elimination from interface requirement alone tracks with our screening on a 48V telecom rectifier project — but the hidden cost hit comes after that cut, when the remaining standalone parts tend to cluster in the $0.18-0.24 range versus $0.35-0.55 for I²C variants, and the BOM savings look attractive until you’re two board revisions in because you can’t read back fault registers during field failure analysis. We’ve started treating I²C as a fixed design requirement regardless of application complexity, because the $0.15/unit premium is trivially recoverable against a single warranty RMA investigation.
The UVLO threshold point is worth expanding on for anyone doing 1S LFP work — we’ve seen charging ICs where the default UVLO sits at 2.5V, well below LFP’s practical recovery floor, so a deeply discharged cell that’s actually damaged will still pass the hardware gate and enter CC phase. We ended up adding a firmware pre-check in our BMS that polls cell voltage via I²C before enabling the charger enable pin, rejecting anything under 2.8V as a soft fault requiring manual reset rather than an automatic retry cycle.