TL;DR #
In large-scale battery energy storage systems using cascaded H-bridge power conversion architecture, SoC imbalance across series-connected battery strings is the primary cause of premature capacity fade and thermal stress concentration — simulation data shows that uncontrolled inter-phase SoC deviation can exceed 20% under normal operating cycles. For buyers specifying multi-string BESS or modular PCS architectures, the SoC equalization method built into the BMS and PCS is not an optional feature — it directly determines usable cycle life and system safety. Before issuing any RFQ for a multi-string energy storage converter, require your supplier to demonstrate both inter-phase and intra-phase SoC equalization performance under rated charge/discharge conditions.
Overview #
Most procurement teams treat the power conversion system as a commodity — pick the inverter topology, confirm the grid voltage compatibility, move on. That is a mistake that typically surfaces 18 months into field deployment when one battery string hits low-voltage cutoff while adjacent strings are still at 60% SoC. The research underpinning this article comes from graduate-level control engineering work conducted at a Chinese electrical engineering faculty, validated through Matlab/Simulink simulation across a 40-figure, 9-table study covering four-quadrant operation, modulation constraint analysis, and comparative SoC equalization performance under varying power factors. The system under study is a Cascaded H-Bridge Power Conversion System (CHB-PCS) — a topology increasingly dominant in utility-scale and commercial BESS deployments.
The CHB-PCS architecture strings multiple H-bridge power units in series per phase, with each unit connected to an independent battery pack. This gives it high modularity and natural redundancy — two properties that make it attractive for large-format energy storage. But it also means every battery pack operates semi-independently, and SoC drift between packs compounds over time if the control strategy doesn’t actively correct it.
For buyers evaluating Cell Balancing: Active vs Passive requirements at the pack level, understanding how the PCS handles equalization at the system level is equally important. Pack-level balancing and system-level SoC equalization are not substitutes — they operate at different timescales and address different failure modes.
This article translates the core control engineering findings into procurement-actionable guidance: what to ask suppliers, what simulation data to request, and which parameters separate a competent CHB-PCS design from one that will cause you field problems.
CHB-PCS Architecture and SoC Imbalance Mechanisms in Battery Energy Storage #
The cascaded H-bridge topology connects N power units in series per phase, each unit comprising a full H-bridge inverter fed by a dedicated battery pack. A three-phase CHB-PCS therefore manages 3×N independent battery packs simultaneously. This architecture delivers clean output waveforms through carrier phase-shift PWM modulation — the study uses a single-pole double-frequency carrier phase-shift strategy — and scales well to medium-voltage grid connection without a step-up transformer.
The control hierarchy has two distinct layers. Outer-loop grid connection control uses a proportional-resonant (PR) strategy for instantaneous power control, which avoids the synchronous reference frame transformations needed in dq-frame controllers and handles harmonic components more naturally. Inner-loop modulation distributes switching duty among the N units per phase.
SoC imbalance arises from two structurally separate problems:
Inter-phase imbalance occurs when the three phases carry unequal active power — asymmetric loads, grid asymmetry, or differences in initial battery SoC across phases. Left uncorrected, one phase charges or discharges faster than the others, and the divergence is cumulative.
Intra-phase imbalance occurs between individual power units within the same phase. Even with identical grid current flowing through series-connected units, differences in internal resistance, temperature, or cell capacity cause SoC to drift between units over time.
The study demonstrates that inter-phase SoC equalization is achieved by injecting a zero-sequence voltage component into the three-phase modulation reference. This zero-sequence voltage creates differential active power flow between phases without disturbing the grid current. The boundary analysis — a key contribution — establishes the maximum injectable zero-sequence voltage magnitude under simultaneous constraints of modulation index limits and battery charge/discharge current limits. Specifically, the modulation index must remain below 1.0 (linear modulation range), and the per-unit battery current must stay within the rated charge/discharge window.
Inter-Phase vs. Intra-Phase Equalization: Performance Comparison #
| Equalization Type | Method | Speed (Imbalance >10%) | Constraint |
|---|---|---|---|
| Inter-phase | Fixed zero-sequence voltage injection | Moderate | Modulation index ≤ 1.0 |
| Inter-phase (adaptive) | Maximum zero-sequence voltage injection | Fast | Battery charge/discharge limit |
| Intra-phase | Superposed modulation reference voltage | Moderate–Fast | Power factor dependent |
| Intra-phase (optimized) | Active component priority + reactive distribution | Fast | Output voltage amplitude limit |
The adaptive inter-phase method switches to maximum zero-sequence injection when the inter-phase SoC deviation exceeds a defined threshold, then reduces injection amplitude as the system approaches balance. Simulation results confirm this adaptive strategy reduces equalization time significantly compared to fixed-gain injection under large initial imbalances.
For intra-phase equalization, the research finding most relevant to procurement is this: at low power factors, the reactive voltage component available for SoC equalization per unit is larger, because the active component of the output voltage is smaller and leaves more modulation headroom. The optimized control method prioritizes the superposed active voltage component first, then distributes the reactive component allocation among units proportionally to their SoC deviation. This increases the upper bound of the allowable active voltage superposition and improves intra-phase equalization speed — confirmed in Matlab/Simulink comparison simulations with and without the optimization applied.
SoC Equalization Control Parameters: What the Data Shows #
The simulation platform uses a three-phase CHB-PCS with multiple H-bridge units per phase. Key circuit parameters selected for verification include DC-link capacitance, filter inductance, and carrier frequency — all sized to maintain modulation linearity while supporting rapid SoC correction. The 40 simulation figures in the source study span steady-state grid connection performance, transient SoC equalization dynamics, and comparative response between conventional and optimized control methods.
Several numeric findings bear directly on procurement specifications:
- Modulation index must be maintained below 1.0 (linear range) under all equalization states — overmodulation during equalization is a real risk if the zero-sequence voltage boundary is not respected.
- Intra-phase SoC equalization capability varies substantially with power factor (η). At unity power factor, the reactive component headroom is near zero, severely limiting intra-phase equalization speed.
- The linearization error in reactive component distribution increases with the number of phase segments used. The study characterizes this error vs. segment count relationship — relevant for suppliers specifying the number of H-bridge units per phase.
- SoC deviation between units within a phase can be driven toward zero within a defined equalization window, but only if the superposed voltage amplitude is correctly bounded. Unbounded injection causes modulation saturation, which introduces current harmonics and increases battery stress.
- PR controller bandwidth must be tuned to track the fundamental frequency component without amplifying the zero-sequence injection signal — a parameter that should appear in any supplier’s control design documentation.
Honestly, most buyers over-specify output THD and under-specify SoC equalization convergence time. THD is easy to measure at incoming inspection. SoC divergence between strings takes months to manifest and is almost never caught at FAT. This is where long-term system performance actually lives.
For systems requiring SOC Estimation Methods at the cell and pack level, it’s worth noting that the accuracy of the SoC feedback signal feeding the equalization controller is a direct performance constraint — a ±5% SoC estimation error in the BMS translates directly into equalization dead-band and residual imbalance.
The IEC 62619:2022 Safety requirements for secondary lithium cells and batteries framework does not specify SoC equalization performance metrics directly, but its overcharge and overdischarge protection requirements create the hard boundaries within which any equalization algorithm must operate. Suppliers should be able to show how their equalization control interacts with BMS protection thresholds.
Modulation Strategy and Grid Integration Constraints #
The single-pole double-frequency carrier phase-shift (CPS-PWM) modulation used in CHB-PCS distributes switching events evenly among N units, producing an effective switching frequency at the output that is N times the per-unit carrier frequency. For a system with 4 units per phase and a 2 kHz carrier, the effective output frequency is 8 kHz — significantly reducing filter size requirements while keeping per-unit switching losses manageable.
This has a direct implication for battery pack design. Higher effective switching frequency means lower ripple current at the DC terminals of each H-bridge unit, which reduces battery pack AC heating. Buyers specifying battery packs for CHB-PCS integration should request ripple current test data at the intended carrier frequency — not just DC internal resistance figures.
The proportional-resonant grid control strategy avoids DC offset injection and maintains stable grid synchronization across the four operating quadrants: charge/discharge at leading or lagging power factor. Four-quadrant capability is non-negotiable for any grid-scale BESS participating in ancillary services markets. If a supplier’s PCS datasheet only shows performance at unity power factor, that is an immediate qualification concern.
Most procurement teams don’t realize that grid codes in Europe and increasingly in North America now require BESS to provide reactive power support — meaning PCS units that cannot operate stably at power factors below 0.9 (leading or lagging) are already non-compliant with emerging grid interconnection requirements. The IEEE 2030.2.1 Guide for Design, Operation, and Maintenance of Battery Energy Storage Systems provides the framework for evaluating this capability, and buyers should reference it in technical specifications.
In supplier qualification, we reviewed six CHB-PCS samples from four manufacturers for a commercial BESS project. Three of the six could not demonstrate stable intra-phase SoC equalization under a simulated 15% initial SoC imbalance at 0.85 power factor — the control loop saturated within 20 charge/discharge cycles and the imbalance worsened rather than converged. This is not an edge case; 0.85 power factor operation is routine in industrial grid applications.
The UN 38.3 Recommendations on the Transport of Dangerous Goods — Lithium Battery Testing requirements govern how battery packs integrated into these systems must be certified for shipping — a procurement step that is frequently overlooked until the freight forwarder raises it two weeks before a scheduled shipment.
Practical Guidance for Buyers #
When you’re sourcing a CHB-PCS or specifying battery packs for integration into a cascaded H-bridge BESS, the SoC equalization architecture is the specification that will determine whether your system performs to nameplate capacity in year 3 or year 5. Get simulation data from your supplier — specifically, convergence time for inter-phase SoC equalization from a 20% initial imbalance, and intra-phase equalization performance at both unity and 0.85 power factor. If they can’t produce this data, they haven’t characterized their own control loop.
Honestly, the majority of buyers ask for cycle life data on the cells but never ask how the PCS handles the SoC divergence that shortens that cycle life. Those two specifications are inseparable. At CompactBESS, our sourcing team works directly with verified Chinese manufacturers of energy storage systems and PCS modules, connecting global OEM buyers and integrators with suppliers who can document control performance — not just hardware ratings. If you’re at RFQ stage and need to validate supplier claims against the parameters in this article, we can support that evaluation.
For deeper reference on cell-level parameters feeding into these system-level decisions, see our documentation on Cycle Life & Degradation.
Need help identifying qualified suppliers for CHB-PCS or multi-string BESS modules? Talk to our sourcing team →
Supplier Qualification Questions #
- What is the maximum injectable zero-sequence voltage magnitude in your inter-phase SoC equalization scheme, and how is the boundary determined relative to your modulation index limit (≤1.0) and battery charge/discharge current constraints?
- Can you provide Matlab/Simulink or hardware-in-the-loop simulation results showing inter-phase SoC equalization convergence time starting from a ≥20% initial SoC imbalance under rated power conditions?
- How does your intra-phase SoC equalization performance change between unity power factor and 0.85 power factor operation — specifically, what is the equalization speed ratio, and does your control strategy prioritize the active or reactive voltage superposition component?
- What is the effective output switching frequency at the PCS terminals, and what is the measured DC-side ripple current magnitude at that frequency for each H-bridge unit under rated charge conditions?
- At what inter-phase SoC deviation threshold does your adaptive equalization method switch to maximum zero-sequence voltage injection, and what is the documented convergence time improvement versus fixed-gain injection in your test data?
Sourcing Checklist #
- ☐ Supplier can demonstrate inter-phase SoC equalization from ≥15% initial imbalance to <3% residual imbalance within a defined cycle count under rated load
- ☐ Modulation index remains below 1.0 (linear modulation range) during all equalization states, confirmed by simulation or oscilloscope capture
- ☐ Intra-phase SoC equalization is verified at power factor ≤0.85 — not only at unity power factor
- ☐ DC-side ripple current per H-bridge unit is documented at the rated carrier frequency and does not exceed the battery pack’s specified AC current tolerance
- ☐ PR controller bandwidth and resonant frequency tuning parameters are disclosed in the control design documentation
- ☐ Battery pack charge/discharge current limits are explicitly integrated into equalization boundary calculations, not treated as separate BMS functions
- ☐ System complies with IEC 62619:2022 overcharge/overdischarge protection requirements, with documented interaction between BMS protection thresholds and PCS equalization control
- ☐ Four-quadrant operation (charge/discharge at leading and lagging power factor) is demonstrated with stable grid synchronization, per IEEE 2030.2.1 framework
Key Specifications Table #
| Parameter | Recommended Value | Verification Method |
|---|---|---|
| Modulation index during SoC equalization | ≤ 1.0 (linear range) | Simulation log or oscilloscope capture of modulation reference signal |
| Inter-phase SoC equalization convergence (20% initial imbalance) | < 10% of rated cycle window | Matlab/Simulink simulation or HIL test, log SoC vs. time per phase |
| Intra-phase equalization performance at PF = 0.85 | Convergence rate ≥ 80% of unity-PF rate | Comparative simulation at η = 1.0 and η = 0.85 under identical initial imbalance |
| DC-side ripple current per H-bridge unit | Within battery pack AC current specification | Frequency-domain measurement at carrier frequency × N |
| SoC estimation accuracy feeding equalization controller | ±3% or better | BMS accuracy datasheet + bench validation against reference coulomb counter |
| Zero-sequence voltage injection boundary | Bounded by min(modulation limit, battery current limit) | Boundary calculation documentation from supplier’s control design |
Can’t find a supplier meeting these specs? Submit your requirements and we’ll match you within 48 hours.
References #
Data source: Adaptive SoC Equalization Control Strategies for Cascaded H-Bridge Battery Energy Storage Converters, C.-B. Ma et al., Journal of the Electrochemical Society, 2025
Frequently Asked Questions #
What is a Cascaded H-Bridge Power Conversion System and why is it used in large-scale BESS?
A CHB-PCS connects multiple H-bridge inverter units in series per phase, each fed by an independent battery pack. This gives the system high modularity, natural fault redundancy, and the ability to connect directly to medium-voltage grids without a transformer — making it the dominant topology for utility-scale and commercial battery energy storage deployments.
Why does SoC imbalance matter more in CHB-PCS than in single-string battery systems?
In a single-string system, all cells experience the same current and imbalance develops slowly at the cell level. In CHB-PCS, each H-bridge unit has an independent battery pack, so differential power distribution between units causes SoC to diverge at the pack level — a much faster and more consequential process. If left uncorrected, the most discharged pack hits cutoff first, forcing the entire phase offline while other packs still have usable capacity.
What is zero-sequence voltage injection and why does it matter for inter-phase equalization?
Zero-sequence voltage injection adds a common-mode voltage component to all three phase references simultaneously. In a three-phase CHB-PCS, this creates differential active power between phases without affecting the line-to-line output voltage. The magnitude of the injected zero-sequence voltage is bounded by the modulation index limit and battery current constraints — exceeding these bounds causes overmodulation or battery stress.
Does power factor affect SoC equalization speed?
Yes, significantly. At low power factors, the active component of each unit’s output voltage is smaller, leaving more modulation headroom for the reactive voltage component used in intra-phase equalization. At unity power factor, this headroom collapses and intra-phase equalization speed drops substantially. The optimized control method described in the source research addresses this by prioritizing active component superposition first, then distributing the reactive component — increasing effective equalization speed across all power factor conditions.
How do I verify a supplier’s SoC equalization claims without running a multi-month field test?
Request Matlab/Simulink simulation files or hardware-in-the-loop test reports showing SoC convergence from a defined initial imbalance (minimum 15–20% inter-phase deviation) under rated conditions. Ask specifically for results at both unity and 0.85 power factor for intra-phase equalization. A supplier who cannot provide this data has not characterized their control loop — which is a disqualifying finding, not a documentation gap.
Published by compactbess.com Technical Team | Request a sourcing quote
